1. Field of the Invention
This invention relates to a data readout circuit for memory devices, and more particularly to an electrically programmable read only memory device.
2. Description of the Related Art
A conventional readout output circuit having a sense circuit is explained below.
The readout output circuit is mainly constructed by memory cell array, a load circuit, dummy transistors, dummy cells and a sense amplifier circuit. In this case, the dummy cell is formed with the same construction as that of each of cells constituting the memory cell array.
In the operation of the readout output circuit, one of a plurality of word lines is selected according to a row address supplied from the exterior and the content of a memory cell which is connected to the selected word line is output to a bit line. Further, one of a plurality of column decoding lines is selected according to a column address signal, a column selector connected to the selected column decoding line is rendered conductive and the memory content of the memory cell output to the bit line is supplied to the first input terminal of the sense amplifier. In a case where the selected cell is an OFF cell which is always set in the nonconductive state, the potential of the first input terminal (Vin.sub.(OFF)) is determined by the load circuit. On the other hand, in a case where the selected cell is an ON cell which can be in the conductive state when the word line voltage rises over the threshold voltage of that cell, the voltage of the first input terminal (Vin.sub.(ON)) is determined by the cell current conducted by the ON cell. The voltage of the second input terminal of the sense amplifier (Vref) is set to the center between the two voltage Vin.sub.(OFF) and Vin.sub.(ON) by the dummy cell and another load circuit for the dummy cell. The sense amplifier is used to amplify a potential difference between the first input terminal and the second input terminal, and it outputs the memory content of the selected memory cell.
In the data readout circuit for the above memory cell array, it is required to enhance the data readout speed to meet the recent technical requirements and the following methods may be considered as a method for satisfying the above requirements. That is, the methods include a method for enhancing the sensitivity of the sense amplifier and a method for enhancing the discharging speed of charges stored on the bit line by increasing a permissible current (cell current) in the memory cell.
However, when the cell current is increased, the power consumption of the memory cell is increased and the pattern area of the memory cells is increased so that the chip size of the memory will be increased. Thus, the method of enhancing the operation speed of the readout output circuit by increasing the cell current in the memory cell has a limitation and it is required to propose a method for effectively enhancing the operation speed.